This invention relates to semiconductor devices and methods of manufacture, and more particularly to protecting the gate insulator of an MOS type of field-effect transistor from the effects of over-voltage or the like.
In microelectronic technology, semiconductor-insulator-semiconductor structures are widely used, as in the polysilicon-gate metal-oxide-semiconductor field-effect transistor (MOSFET) employed in most memory and microprocessor devices made today. A voltage is applied to the gate electrode in these devices to create an inversion layer of charge carriers in the substrate, beneath the gate. The charge carriers form a conductive path between source and drain regions, giving rise to current flow when drain bias is applied. The voltages applied to the gate are chosen to ensure an adequately high inversion charge density when the transistor is on, and low leakage current when the transistor is off. Application of this gate voltage creates an electric field in the gate insulator, however, and if the field is sufficiently high, charge carriers can tunnel into or through the insulator. The interaction of these charge carriers with the insulator is responsible for several failure mechanisms, generally known as time-dependent dielectric failure. Due to the physical relationship between tunneling current and electric field, the lifetime of the integrated circuit device with respect to time-dependent failures decreases exponentially with increasing electric field in the insulator. As a result, small increases in gate voltage can lead to large reductions in lifetime of the devices due to time-dependent failures.
The time-dependent failure lifetime of a particular integrated circuit device depends upon the device structure and the applied bias conditions. Because electrons tunnel into the gate insulator more easily than holes, the time-dependent failure lifetime is shorter in situations where electrons are the tunneling species. This occurs most frequently in N-channel devices biased into inversion, i.e., a positive voltage applied between the gate and source.
Due to power supply ringing, bond wire inductance, capacitive coupling and other effects, the gate voltage can exceed its nominal range by very significant amounts. It is not uncommon to experience voltage transients exceeding the nominal power supply voltage by more than one volt, which is substantial in integrated circuit devices using 5 V or 3 V power supplies. Because of the exponential dependence between time-dependent failure lifetime and gate voltage described above, the lifetime can be dominated by these voltage transients.
Methods previously employed to deal with the problem of time-dependent dielectric failure fall into three categories. One is lowering the supply voltage, which also lowers the magnitude of most of the transients. Another is increasing the thickness of the gate insulator or improving the quality of the gate insulator so that it degrades more slowly. The third is that of designing the circuit such that transients are minimized.
Lowering the supply voltage and increasing the dielectric thickness are very effective ways to increase the time-dependent failure lifetime. The disadvantage of these techniques is that the associated reduction in inversion charge density leads to a reduction in device performance. Changes in circuit design which minimize transients are also difficult to achieve without a sacrifice in performance. Attempts to increase the robustness of the material used as the dielectric have resulted in improvements which are generally quite small, and alternative dielectrics can introduce other problems such as increased process complexity, reduced yield, and high densities of interface traps.